Phase 70 · physical mapping · first bench experiment · AT-0689 → AT-0700
We stop arguing about space and go build a small electronic network that can tell us we are wrong.
Everything the programme has built so far lives inside mathematics. This page is the design that leaves it: a programmable network of electronic oscillators with local, logged coupling updates, and ten pass/fail metrics locked before a single component is bought. The goal is not spacetime manipulation. It is to physically realize the abstract two-phase moving-doorway architecture and find out whether measured behaviour matches what was written down in advance. Nothing here has been built, run, or measured.
Status
physical evidence: noneExperiment v0.1 — pre-registered, unbuilt, and designed to fail loudly.
PROTOCOL ONLY — NO HARDWARE DATA EXISTS
Locked metrics
10
M1 → M10, fixed before any run
Controls
7
including an intentionally cheating global switch
Declared null
N = 8
no advantage expected or permitted
Physical evidence
NONE
Bench wiring schematic · stage 0 · 16 oscillators · degree 3
design targets · not measurements- W1Sixteen oscillator nodes on a bounded-degree-3 graph: 24 physical links, each carrying one programmable coupling element. Physical degree is fixed in copper and never changes during a run.
- W2Each coupling element exposes a single digital weight register. C0 is the low-weight baseline; C* is a transient high-weight state. The graph is the same in both phases — only weights move.
- W3Every node exposes an analogue probe point to a synchronised ADC channel, plus a second channel for the coupling-element drive, giving 32 capture channels at Stage 0.
- W4The controller is partitioned in firmware so that the logic for node i may read only node i's own state, its ≤3 neighbours, and an address prefix. This partition is the anti-cheat boundary and it is audited statically as well as from the log.
- W5Four supply rails are physically separate from the start: control logic, oscillators, coupling elements, and the restoration drive. Energy is never apportioned by subtraction.
- W6Fault injection sits in series with eight of the links and in the power gate of four nodes, driven from the same clock as the log.
Solid ring links and dashed chords are physical copper and never change. Only coupling WEIGHTS move between C0 and C*. The highlighted path is an illustrative doorway route, not a measured one.
Illustrative run timeline · trigger → moving window → arrival → recovery
physical evidence: none- 1 · Trigger
Local seed crosses threshold at node 0.
- 2 · Moving window
A bounded active set advances along the address route.
- 3 · Payload arrival
Four-component waveform captured at the destination.
- 4 · Recovery
Couplings fall back to C0 behind the front. No global reset.
ANIMATION OF THE PROTOCOL'S EXPECTED SHAPE. No instrument produced this trace.
Preregistration scorecard · ten locked metrics
physical evidence: noneAn intentional local seed crosses a reproducible activation threshold. Below-threshold perturbations launch no doorway above a false-trigger ceiling declared before the run.
fails if Response is smooth with no threshold, or below-threshold noise launches doorways above the ceiling.
Instrument — Amplitude sweep, 200+ trials per amplitude, operator blind to outcome.
Maximum simultaneously active nodes stays at or below c · log2 N, with c fixed before the run; the initial target window is equivalent to about four nodes at small N.
fails if Active count grows like O(N) — a global avalanche rather than a moving doorway.
Instrument — Synchronised per-node ADC capture, active = amplitude above declared activation band.
The controller may implement only the same local neighbour update law at every node. No global path command, no destination-wide broadcast, no precomputed per-trip shortest path.
fails if Any coupling write depends on state outside the writing node's bounded neighbourhood and address prefix.
Instrument — Static audit of controller firmware plus timestamped control-write log.
A structured waveform with at least four independent components, compared before and after transit against an identity-error tolerance predefined for each component.
fails if Any component exceeds tolerance, or a single tone is substituted for the structured payload.
Instrument — Multi-channel capture at source and destination, component-wise error metric.
Total clock starts at trigger. C0 baseline and doorway mode are compared on identical hardware and topology. N = 8 is an explicit null where no advantage is expected; N = 16 / 32 / 64 test the trend.
fails if Doorway latency fails to fall below the C0 baseline at N = 16 and above, or an advantage is claimed at N = 8.
Instrument — Common time base, trigger-to-arrival timestamps on both modes, interleaved runs.
All coupling and state variables return within a declared baseline tolerance WITHOUT a global reset.
fails if Any global reset command appears in the log, or variables settle outside tolerance.
Instrument — Coupling-register dump and per-node state capture through the recovery window.
Supply energy measured separately for control, oscillators, coupling elements and restoration. Once hardware exists, no normalized proxy is permitted anywhere on this page.
fails if Energy is reported as a normalized count, or the four rails are lumped into one figure.
Instrument — Four instrumented supply rails, integrated current-sense over the whole transfer window.
Edge and node failures are injected DURING transit; local repair and recovery are logged as they happen.
fails if Recovery requires a global rebuild, or the log cannot show the repair was locally decided.
Instrument — Switched link cut-outs and node power-gates on a scripted injection schedule.
Two, four and eight concurrent payloads at N ≥ 32, tracking p50 and p95 latency and every conflict event.
fails if p95 collapses, or conflicts are resolved by any central arbiter.
Instrument — Concurrent source triggers, per-flow timestamps, conflict counters in the log.
Every control write is timestamped. Any nonlocal or global reconfiguration DISQUALIFIES the run from counting as doorway evidence.
fails if The log is incomplete, or a single global reconfiguration write is found.
Instrument — Append-only control-write log, audited independently of the narrative.
Anti-cheat control-write log
physical evidence: none| t (µs) | writer node | link | weight | scope |
|---|---|---|---|---|
| 0 | 0 | 0–1 | 0.05 → 0.82 open | LOCAL |
| 12 | 1 | 1–9 | 0.05 → 0.84 open | LOCAL |
| 24 | 0 | 0–1 | 0.82 → 0.05 close | LOCAL |
| 30 | 9 | 9–10 | 0.05 → 0.83 open | LOCAL |
| 42 | 1 | 1–9 | 0.84 → 0.05 close | LOCAL |
| 48 | 10 | 10–11 | 0.05 → 0.81 open | LOCAL |
| 60 | 9 | 9–10 | 0.83 → 0.05 close | LOCAL |
| 72 | 10 | 10–11 | 0.81 → 0.05 close | LOCAL |
ILLUSTRATIVE LOG SHAPE — these rows show what an admissible log looks like, not what any instrument recorded. A single row stamped GLOBAL would disqualify the run.
Scaling design space · N = 8, 16, 32, 64
design targets · not measurementsAt eight nodes the doorway overhead exceeds the ordinary chain. NO ADVANTAGE IS EXPECTED and none may be reported. This size exists to show the architecture does not win everywhere.
First size where the design target predicts any advantage at all, and only a slim one.
Stage 1 build. Bounded-degree graph, concurrency sweep begins here.
Stage 2 build, physical or time-multiplexed. Time-multiplexed nodes are EFFECTIVE, not physical, which weakens any localization reading.
| N | degree-3 edges | measurement channels | control updates / tick | target max active fraction | ordinary latency | doorway target |
|---|---|---|---|---|---|---|
| 8 | 12 | 16 | 12 | 50.00% | 4 | 4.8 |
| 16 | 24 | 32 | 24 | 25.00% | 8 | 6.4 |
| 32 | 48 | 64 | 48 | 12.50% | 16 | 8.0 |
| 64 | 96 | 128 | 96 | 6.25% | 32 | 9.6 |
These are EXPERIMENT DESIGN TARGETS and illustrative model expectations in arbitrary latency units. They are not measured hardware data and there is no measured column, because no measurement exists.
Controls · run interleaved in a pre-declared random order
| id | control | what it separates |
|---|---|---|
| K1 | C0 only — latent couplings disabled | Establishes the ordinary-route baseline on the same hardware. |
| K2 | Global switch control — intentionally cheating | Establishes the upper bound of conventional switching performance, so a doorway result can be placed against it honestly. |
| K3 | Random local switching at matched control writes and energy | Separates structured local law from mere reconfiguration activity. |
| K4 | Shuffled destination addresses | Detects a route that works regardless of the address it claims to follow. |
| K5 | Below-threshold trigger | Measures the false-trigger floor that M1 is scored against. |
| K6 | Same payload over the ordinary route | Separates payload fidelity from doorway transport. |
| K7 | Frozen doorway state, recovery suppressed | Isolates the cost of restoration from the cost of transport. |
Success classification · fixed before the run
HARDWARE ANALOG FAIL
No reproducible moving doorway. The architecture does not survive contact with a circuit and the toy result stands alone.
PROGRAMMABLE NETWORK EFFECT ONLY
An effect exists, but it requires global switching or path scripting. That is conventional network engineering, not a doorway.
LOCAL TWO-PHASE ANALOG CANDIDATE
Localized thresholded propagation, payload delivery and restoration under a purely local law, surviving every control. A statement about a circuit.
SCALING ANALOG CANDIDATE
Grade C, plus latency and active-footprint trends that continue favourably with N across the tested sizes only.
There is deliberately no grade above D. No outcome of this experiment can be classified as evidence about spacetime, distance, or fundamental physics, and no such category will be created.
Experiment v0.1 · bill-of-materials categories
| category | role | stage 0 qty | requirement |
|---|---|---|---|
| Oscillator node | One tunable electronic oscillator per node — the substrate element S. | 16 | Stable free-running frequency, accessible phase/amplitude probe point, identical part across all nodes. |
| Programmable coupling element | Sets the weight of each link between two nodes: C0 baseline low, C* transient high. | 24 (degree-3) | Digitally settable coupling strength, monotonic response, settling time far below one propagation tick. |
| MCU / FPGA controller | Runs the identical local update law at each node and writes coupling registers. | 1 FPGA or 16 per-node MCUs | Deterministic tick, per-node scope limited in firmware to its own bounded neighbourhood and address prefix. |
| ADC / scope channels | Captures per-node state for the active-count, latency and payload-identity metrics. | 32 channels | Synchronised sampling on a common time base, bandwidth several times the oscillator frequency. |
| Power measurement | Four separated supply rails: control, oscillators, coupling elements, restoration. | 4 instrumented rails | Current-sense with integration over the transfer window; no rail may be inferred by subtraction. |
| Fault injection | Cuts links and gates nodes during transit for the fault-tolerance metric. | 8 switched cut-outs | Scriptable, timestamped on the same clock as the control-write log. |
| Logging host | Append-only capture of every control write, trigger, injection and capture frame. | 1 | Write-once storage, clock-synchronised, audited independently of whoever ran the experiment. |
Component choices are GENERIC categories. No part number, vendor, price or availability has been sourced or verified, and none should be inferred from this table.
Data schema · append-only capture
run_id · utc_start · N · topology_hash · firmware_hash · mode (C0 | doorway | control_id) · declared thresholds · operator_blind flag
t_ns · writer_node · target_link · old_weight · new_weight · justifying_neighbour_state · address_prefix_used
t_ns · node_id · amplitude · phase · active_flag (vs declared activation band)
t_ns · component_index (≥4) · amplitude · phase · source_or_destination
t_ns · rail (control | oscillator | coupling | restoration) · instantaneous_power · integrated_joules
t_ns · injected_element · type (link_cut | node_gate) · restored_at_ns · repairing_nodes
flow_id · trigger_t_ns · arrival_t_ns · conflicts · p50 · p95
metric_id (M1…M10) · locked_criterion · observed · PASS | FAIL | NOT MODELLED · auditor
Step-by-step test protocol
- 01
Seal the preregistration
Publish c for M2, the false-trigger ceiling, the per-component identity tolerances, the baseline restoration tolerance and the control ordering. Hash the document. Nothing below may change these.
- 02
Build and characterise C0
Bring up 16 nodes at baseline coupling. Measure free-running frequencies, drift, noise floor and the ordinary chain latency across the declared endpoint pairs.
- 03
Audit the firmware partition
Statically verify that no node's update law reads outside its bounded neighbourhood and address prefix. A failure here stops the experiment; it is not a finding, it is a build defect.
- 04
Threshold sweep (M1)
Sweep trigger amplitude with 200+ blind trials per level, including the below-threshold control K5. Fit the formation probability curve.
- 05
Single-payload doorway runs (M2, M4, M5, M6)
At N = 8 first, as the declared null. Then 16. Capture active counts, four-component payload fidelity, trigger-to-arrival latency and the restoration tail.
- 06
Interleaved controls (K1–K7)
Run every control in the pre-declared random order, interleaved with doorway runs so drift cannot masquerade as an effect.
- 07
Energy runs (M7)
Repeat the transfer with all four rails integrated separately, including a recovery-suppressed K7 pass to isolate restoration cost.
- 08
Fault injection during transit (M8)
Cut links and gate nodes mid-flight on the scripted schedule. Log which nodes repaired and how far the repair propagated.
- 09
Scale to 32, then 64 (M5 trend)
Repeat steps 5–8. Report trends only; no exponent may be fitted from four sizes and none will be.
- 10
Concurrency (M9)
Two, four and eight simultaneous payloads at N ≥ 32. Record p50, p95 and every conflict event.
- 11
Seal the log and audit (M10)
Freeze the append-only log. An auditor who did not run the experiment checks every control write against the locality rule. One global reconfiguration disqualifies the run.
- 12
Score and publish, pass or fail
Fill the verdict stream against the sealed criteria, assign grade A–D, and publish the result unchanged. A failure is published with the same prominence as a pass.
For a ten-year-old
Now we stop asking the computer to pretend. We build a real electronic network and see whether a tiny moving doorway can appear for real. If the hardware disagrees, we change the theory — not the result.