Phase 71 · pre-hardware falsification · pipeline validation
We cannot test the hypothesis yet, so we tested the scoreboard that will judge it.
Three synthetic worlds where we already know who should win: nothing happening, an ordinary programmable switch, and the two-ruler pattern we are hunting. A thousand blinded datasets each. The first rule we wrote was brittle enough to hand the ordinary switch our headline label, so we killed it and froze a slope-and-endpoint rule instead — before any hardware existed. Physical evidence remains NONE.
Status
synthetic data · pipeline validation · not evidencePIPELINE VALIDATION UNDER SYNTHETIC WORLDS · NO HARDWARE · PHYSICAL EVIDENCE NONE
COMPUTATIONAL RESULT (SYNTHETIC DATA, ASSUMED NOISE MODEL)
Every number on this page is generated from assumed distributions we wrote ourselves. A high classification rate says our scoreboard is hard to fool by the failure modes we imagined. It says nothing whatsoever about whether the physical effect exists.
Phase 71b · third ruler promoted
The two-ruler test is necessary but not sufficient.
THE TWO-RULER TEST IS NECESSARY BUT NOT SUFFICIENT. Three ordinary mechanisms — adaptive caching, a hidden central scheduler, and a precomputed shortcut table — pass both scaling rulers in roughly 95% of synthetic run sets. A third ruler, mechanism locality and auditability, is now a hard gate.
Evil twins
Three ordinary mechanisms wearing our result as a costume
Each mimic is a mechanism nobody would call exotic. We chose their target means specifically so that both frozen scaling rulers are satisfied. Over 500 synthetic run sets each, they pass the old rule roughly 95% of the time.
| Conventional mimic | Passes under two rulers | Passes under three rulers | Verdict now returned |
|---|---|---|---|
| Adaptive caching | 477 / 500 (95.4%) | 0 / 500 | CONVENTIONAL / UNAUDITABLE MECHANISM |
| Hidden central scheduler | 483 / 500 (96.6%) | 0 / 500 | CONVENTIONAL / UNAUDITABLE MECHANISM |
| Precomputed shortcut table | 480 / 500 (96.0%) | 0 / 500 | CONVENTIONAL / UNAUDITABLE MECHANISM |
The controller remembers routes it has already used and replays them. Nothing exotic — a lookup cache with a hit rate that improves as the machine runs.
Cache hits shorten trips (latency ratio falls) and skip intermediate wake-ups (active fraction falls). Both rulers move the 'right' way.
Caught by — M3 · no consultation of stored end-to-end route state; M7 · topology relabeling destroys cache keys.
A single privileged process holds a global congestion map and hands each node its next move. Every node looks local from the outside.
Centralized planning is genuinely efficient: it routes around congestion and only wakes the nodes it needs, so both rulers fall smoothly with N.
Caught by — M1 · per-node attributed event log; M3 · no centralized congestion map; M5 · any global read voids the run.
An all-pairs shortcut table is compiled offline and burned into firmware. At run time the controller performs one table read.
A precomputed shortcut is the cheapest possible trip and touches almost nothing, so it maximises both rulers at once — the strongest evil twin.
Caught by — M3 · no all-pairs route table; M6 · frozen firmware hash; M9 · unseen topology loaded after freeze.
Third ruler · mechanism locality and auditability
Ten conditions, frozen before hardware exists
A would-be analogue candidate must now prove not only that the two numbers move the right way, but that the mechanism producing them is genuinely local and fully auditable. These conditions are fixed now, while we still have no data to bias them.
Every read and every write performed by any node or controller is logged with a timestamp and the identity of the node that performed it. No anonymous events.
A node or controller may access only: its own state, the states of directly connected neighbours, compact prebuilt LOCAL address metadata, and the destination token/address the protocol permits it to carry.
No global topology map, no all-pairs route table, no centralized congestion map, no precomputed end-to-end shortcut table, and no hidden scheduler may be read at any point during a run.
No access to states that have not yet occurred, to oracle predictions, or to a simulated forward run of the machine.
A single prohibited read or write invalidates the ENTIRE run set, not merely the offending sample. No trimming the bad trials.
Controller firmware/software is hashed and published before the first datum is recorded. Any change restarts the campaign.
Topology labels and endpoints are randomly remapped between runs so that a hidden lookup table cannot key off fixed node IDs.
Adaptive-caching and centralized shortest-path firmwares are deliberately submitted to the audit. The audit MUST catch them, or the audit itself fails.
After the firmware freeze, a previously unseen topology is loaded. The controller must still operate using only local rules, with no recompilation.
The behaviour must transfer across independently generated topologies with no retraining and no per-topology parameter tuning.
Three-ruler bench test · verdict engine
| Condition | Verdict |
|---|---|
| Quality gates + R1 + R2 + R3 | ANALOGUE HARDWARE EFFECT CANDIDATE |
| Quality gates + R1 + R2, R3 fails | CONVENTIONAL / UNAUDITABLE MECHANISM |
| Quality gates + R1, R2 fails | CONVENTIONAL SWITCHING-LIKE |
| Anything else | FAIL / NO EFFECT |
Only all three rulers plus the quality gates can yield ANALOGUE HARDWARE EFFECT CANDIDATE. Passing rulers 1 and 2 while failing the audit is now explicitly labelled CONVENTIONAL / UNAUDITABLE MECHANISM — the evil twins live there.
In plain language
Two scoreboards can be fooled by a magician who already knows the maze. So we added a third referee who watches every move and checks that nobody secretly looks at the whole map.
Frozen verdict engine
A pure function. It takes the frozen metric table and returns one of three labels. No analyst input is accepted at verdict time.
- median R_T at N = 16, 32, 64
- median f_active at N = 16, 32, 64
- median payload fidelity at each N
- false-trigger rate at each N
- count of illegal / global controller writes
- quality gate: pass / fail
- latency signature: slope + endpoint
- sparsity signature: slope + endpoint
- verdict label (one of three)
- machine-readable failure reasons
quality + latency, no sparsity → CONVENTIONAL SWITCHING-LIKE
otherwise → FAIL / NO EFFECT
These thresholds are EXPERIMENT-DESIGN CHOICES and preregistered targets. They are not laws of nature, and no physical claim follows from meeting them.
Red team the analysis before the hardware
synthetic data · pipeline validation · not evidenceWe generated 1000 blinded synthetic datasets from each of three worlds where we already know the right answer, at N = 16, 32, 64, with 60 trials per size, and fed them to the frozen verdict engine. This measures how hard our scoreboard is to fool — nothing else.
No effect at all. Latency ratio sits at 1 and the active fraction never falls.
f_active 0.26 · 0.26 · 0.26
A perfectly ordinary programmable switch. It really does get faster — and wakes the same fraction of the machine every time.
f_active 0.28 · 0.27 · 0.26
Both rulers fall together: the trip gets relatively faster while less and less of the machine wakes up.
f_active 0.25 · 0.14 · 0.08
| True world | FAIL / NO EFFECT | CONVENTIONAL SWITCHING-LIKE | CONVENTIONAL / UNAUDITABLE MECHANISM | ANALOGUE HARDWARE EFFECT CANDIDATE | Correct |
|---|---|---|---|---|---|
| NULL | 1000 | 0 | 0 | 0 | 100.0% |
| SWITCH | 38 | 962 | 0 | 0 | 96.2% |
| DOORWAY | 0 | 30 | 0 | 970 | 97.0% |
These are PIPELINE-VALIDATION rates under distributions we assumed. They are not evidence for the physical hypothesis and can never become evidence for it.
Why the adjacent-monotonic rule was rejected
ADJACENT-MONOTONIC: require median R_T and median f_active to fall at every consecutive step, 16 → 32 → 64.
With only three sizes, one noisy median in the middle breaks a strictly monotonic chain even when the underlying trend is strongly downward. The rule throws away the size of the effect and keeps only the sign of two differences, so it is dominated by whichever draw happened to be unlucky.
Fit a slope across log2 N and pair it with an endpoint threshold. The slope uses all three sizes and the magnitude, not just two sign tests. Thresholds fixed in advance; no post-hoc tuning.
REJECTED BEFORE ANY HARDWARE DATA EXISTED — this is a design fix, not a reaction to a disappointing measurement.
| True world | FAIL / NO EFFECT | CONVENTIONAL SWITCHING-LIKE | CONVENTIONAL / UNAUDITABLE MECHANISM | ANALOGUE HARDWARE EFFECT CANDIDATE | Correct |
|---|---|---|---|---|---|
| NULL | 832 | 148 | 0 | 20 | 83.2% |
| SWITCH | 0 | 153 | 0 | 847 | 15.3% |
| DOORWAY | 0 | 0 | 0 | 1000 | 100.0% |
The damaging cell is the conventional-switching row: the brittle rule hands an ordinary programmable switch the analogue-candidate label whenever three noisy medians happen to fall in order. That is exactly the mistake the whole programme exists to avoid.
Robustness sweeps · where the scoreboard degrades
synthetic data · pipeline validation · not evidenceWe vary the assumed latency noise, sparsity noise, trial count and a small systematic timing offset, and record the classification rate for each world. The rule is unchanged throughout — only the world's nastiness changes.
| Axis | Setting | NULL | SWITCH | DOORWAY | Worst |
|---|---|---|---|---|---|
| Latency noise | SD(R_T) = 0.04 | 100.0% | 96.5% | 97.0% | 96.5% |
| Latency noise | SD(R_T) = 0.08 (planning) | 100.0% | 97.0% | 97.0% | 97.0% |
| Latency noise | SD(R_T) = 0.16 | 100.0% | 95.5% | 96.8% | 95.5% |
| Latency noise | SD(R_T) = 0.30 | 100.0% | 87.8% | 96.5% | 87.8% |
| Sparsity noise | SD(f_active) = 0.015 | 100.0% | 97.0% | 97.3% | 97.0% |
| Sparsity noise | SD(f_active) = 0.03 (planning) | 100.0% | 97.0% | 97.0% | 97.0% |
| Sparsity noise | SD(f_active) = 0.06 | 100.0% | 97.0% | 96.8% | 96.8% |
| Sparsity noise | SD(f_active) = 0.10 | 100.0% | 97.0% | 96.5% | 96.5% |
| Trial count | 5 trials / size | 100.0% | 86.8% | 98.5% | 86.8% |
| Trial count | 20 trials / size | 100.0% | 97.8% | 97.5% | 97.5% |
| Trial count | 60 trials / size (planning) | 100.0% | 97.0% | 97.0% | 97.0% |
| Trial count | 200 trials / size | 100.0% | 98.0% | 98.3% | 98.0% |
| Timing offset | +0.00 (none) | 100.0% | 97.0% | 97.0% | 97.0% |
| Timing offset | +0.05 systematic | 100.0% | 88.5% | 96.3% | 88.5% |
| Timing offset | +0.10 systematic | 100.0% | 75.8% | 93.8% | 75.8% |
| Timing offset | +0.20 systematic | 100.0% | 27.8% | 72.3% | 27.8% |
Read the failure modes honestly: the null world is never mislabelled, but a systematic timing offset is the engine's soft spot — it drags the conventional-switching world across the latency line and inflates apparent advantage. Clock calibration is therefore a first-class instrumentation requirement, not an afterthought. Small trial counts hurt the switching row too, which is why the run plan asks for ≥ 20 valid runs per condition.
Negative control · illegal controller write
- — 1 illegal / global controller write(s) — run set invalidated.
One illegal controller write is injected into an otherwise perfect would-be analogue pass. The engine must and does drop it to FAIL / NO EFFECT. There is no severity scale and no judgement call: a single global read or write outside a node's allowed local neighbourhood invalidates the run set.
Data-integrity rules
- No manual exclusions. Ever. A run is dropped only by a preregistered hardware-fault code.
- No smoothing-dependent metric. Medians over raw samples, fixed thresholds, fixed dwell windows.
- Raw timestamps preserved verbatim alongside every derived number.
- Exclusion codes are fixed in advance: instrumentation failure, saturation / clipping, missing samples, clock-sync loss, explicit locality violation.
- Every excluded run ID and its code is published with the valid runs.
- The verdict engine is a pure function of the frozen metric table. No analyst input is accepted at verdict time.
Status reconciliation · stricter record wins
Where a later summary and an earlier recorded experiment disagree, the site keeps the STRICTER recorded evidence. Conversational claims that the multi-user, fault-tolerance and lifecycle gates were fully passed are superseded by the recorded Phase 66-69 verdicts, which are conditional. The hardware programme may proceed as an ANALOGUE EXPERIMENT DESIGN regardless — a bench test of a cost-and-sparsity signature does not require the toy architecture gate to be closed.
| Gate | Recorded state | Why |
|---|---|---|
| Toy Architecture Gate | CONDITIONAL / UNRESOLVED | Holds only under high-utilization reuse assumptions that are ours, not the world's. It is NOT stamped passed. |
| Multi-user scalability (exact fabric) | UNRESOLVED | Phase 66 is the stricter record and it stands: concurrency on the exact fabric was never run inside budget, and the queueing proxy exposed a single-root deadlock. Multi-root dispersion improved the proxy; it did not close the exact-fabric question. |
| Activation-throughput debt | OPEN | Completion never reached 1 under the finite doorway window, and benefit-per-overhead peaked at small K. |
| Fault tolerance | FIRST PASS (MESH) / FAILED (SINGLE-TREE BACKUP) | The redundant multi-tree mesh result stands, and the failed backup-parent design stays visible beside it. |
| Physical evidence | NONE | No hardware exists. Nothing in the analogue experiment design changes this. |