Phase 70 · physical mapping update · bench ready

The hardware to test this already exists — so the plan stops being hypothetical.

Experiment v0.1 was written against imagined hardware. It is now rebuilt against three published, working oscillator platforms: an electronic quadrature-oscillator Kuramoto array with arbitrary weighted and directed coupling, a 28-node hybrid analog-digital Rössler-like network with FPGA-computed coupling, and an optoelectronic time-delay platform that reached large arbitrary topologies. None of them was built to test anything of ours. Together they establish that the substrate, the topology freedom and the instrumentation this architecture needs are buildable today with documented technique.

Status

physical evidence: none

BENCH READY — protocol locked against real platforms, nothing built.

Precedent platforms

published, peer-reviewed, independent of us

Experiment phases

P0 → P7

calibration first, always

First-pass criteria

frozen before any component is bought

Physical evidence

NONE

Published hardware precedents · references

Platform	Citation	Scale	Oscillator	Coupling	Topology	Demonstrated	Use to us	What it does not give us
Experimental Kuramoto platform	Phys. Rev. E 114, L022202 (published 21 August 2026) DOI 10.1103/jpwn-hcwx · arXiv:2608.04119	Scalable electronic array; cost-effective per node	Electronic quadrature oscillators	Nondiffusive coupling, arbitrary weighted and directed	Arbitrary weighted / directed network topologies	Experimentally reproduces global and cluster synchronization phase transitions	PREFERRED NODE. Gives us a documented electronic oscillator with directed, weighted, arbitrarily wired coupling — exactly the substrate S and the C0/C* weight distinction the architecture needs.	Demonstrates synchronization physics, not routing, not thresholded local corridors, and nothing about Adjacency Theory.
Hybrid analog-digital Rössler-like platform	VLSI (2026), article 102700 Hybrid analog oscillators with FPGA-computed coupling	28 analog electronic oscillators	Rössler-like analog electronic oscillators	FPGA-computed Laplacian coupling	Reconfigurable random and small-world topologies	Real-time synchronization and intermittency studies	ALTERNATE NODE if quadrature oscillators are hard to source. Its FPGA-computed coupling is the precedent for our digital coupling stage — but we must restrict that stage to a strictly local update rule, which this platform does not do.	Laplacian coupling is computed centrally. Adopting it unmodified would fail our anti-cheat rule and produce, at best, a grade-B result.
Optoelectronic FPGA time-delay platform	Chaos 27, 121103 (2017) Time-multiplexed optoelectronic oscillator network	Large arbitrary-topology networks via time multiplexing	Optoelectronic time-delay oscillators	FPGA-mediated, time-multiplexed	Arbitrary, reconfigurable at scale	Large arbitrary-topology oscillator networks driven in real time	SCALING PRECEDENT ONLY. Shows how to reach N = 64 and beyond without 64 physical nodes.	Time-multiplexed nodes are EFFECTIVE, not physical. Any localization claim (M2 / P3) weakens sharply on such a platform and must be labelled accordingly.

These three platforms are cited as ENGINEERING PRECEDENT for buildability only. None was designed to test Adjacency Theory, none contains a moving doorway, and none provides any evidence for or against anything in this programme.

Wiring and control architecture · what each layer is allowed to see

physical evidence: none

L0Analog substrate

Quadrature oscillator nodes on a fixed degree-3/4 coupling matrix, with programmable per-edge gain.

MAY SEE — Its own physical state. Nothing is 'told' to this layer except an edge gain.

L1Per-node local law

Analog state estimator + FPGA/MCU state machine running the identical threshold / recovery rule at every node.

MAY SEE — Node i's own state, its ≤4 neighbours' states, and the compact destination address prefix. NOTHING ELSE.

L2Address service (pre-trip only)

Self-organized compact address algorithm, run in the FPGA BEFORE endpoints A and B are chosen.

MAY SEE — The frozen topology. It never runs during a trip and never sees a trip's endpoints.

L3Audit plane

Append-only log of every coupling change, state update, timestamp and origin; four separated supply rails.

MAY SEE — Everything — it is read-only and can issue no write of any kind.

THE ONLY DOWNWARD ARROW IN THIS STACK IS A SINGLE EDGE-GAIN WRITE FROM A NODE'S OWN LOCAL LAW. THERE IS NO PATH BY WHICH A GLOBAL SCHEDULER CAN REACH THE SUBSTRATE. IF ONE APPEARS IN THE LOG, THE RUN IS VOID.

Translation · abstract object → bench object

Abstract object	Bench realization	Hard constraint
Node	Electronic quadrature oscillator, per the 2026 Kuramoto platform. Rössler-like analog oscillator is the accepted alternate if sourcing is easier.	Identical part across all nodes; per-node probe point mandatory.
Substrate S	A FIXED sparse degree-3/4 coupling matrix, realized physically in wiring or digitally in a frozen coupling map. It does not change during a run.	The graph is fixed before the run and hashed into run_meta. Only weights move.
Ordinary phase C0	Only the designated 'ordinary' coupling subgraph is accessible and effective; latent corridor edges sit at baseline weight.	C0 is the comparison baseline for every latency claim.
Local state c_i, r_i	Per-node analog state estimator feeding an FPGA or local MCU state machine. Digital emulation of the local dynamics is accepted for v0.1; if the experiment passes it is replaced by fully analog local dynamics.	Every update may read ONLY the node's own state and its direct neighbours. Enforced in firmware and audited from the log.
Moving doorway C*	A thresholded local coupling-gain enable applied only to next-hop / neighbour edges, opening ahead of the front and closing behind it.	The controller is NOT permitted to globally schedule route activation. A global schedule invalidates the run.
Payload	Phase-coded or amplitude/phase structured waveform with at least four independent components, injected at A and reconstructed at B.	Identity tolerance is set only AFTER P0 noise calibration, then frozen before P4.
Address logic	The self-organized compact address algorithm from the toy architecture. For v0.1 it may run in the FPGA BEFORE A and B are selected.	Per trip, the controller sees only the compact destination address plus local neighbour state. Nothing else.
Write audit	Every coupling change, state update, timestamp and origin is logged append-only.	Any nonlocal controller write during a run invalidates that run outright.

Experiment flow · P0 → P7

P0Calibration
Uncoupled oscillator frequency and phase-noise characterisation; ADC and control-loop latency measurement.
PRODUCES — The noise floor that every tolerance on this page is defined against. Nothing else may be frozen before this exists.
P1C0 baseline
8, 16 and 32 nodes in the ordinary phase only. Full ordinary-path signal latency distribution across declared endpoint pairs.
PRODUCES — The baseline distribution, not a single number — comparisons are distributional.
P2Trigger threshold
Sweep trigger amplitude. Estimate the recruitment curve and the false-trigger curve independently.
PRODUCES — Recruitment curve, false-trigger rate with binomial confidence interval.
P3Moving doorway, no payload
Local threshold and recovery law only. Measure active footprint over time and self-restoration to baseline.
PRODUCES — Active-footprint trace and restoration statistics with no payload confound.
P4Payload
Structured waveform A → B. Compare latency and identity error against C0 on identical hardware.
PRODUCES — Latency delta and component-wise identity error against the tolerance frozen after P0.
P5Scaling
N = 8, 16, 32, then 64 if the platform allows. Test the preregistered latency-scaling DIRECTION only.
PRODUCES — A trend. No exponent, and no asymptotic statement from N ≤ 64.
P6Controls
Globally switched fast path (the positive cheating control), random local coupling changes at matched write count, static latent-path control, and a controller-disabled negative control.
PRODUCES — The null distributions that any doorway result must beat.
P7Faults and concurrency
Edge and node failures injected during transit; 2, 4 and 8 concurrent payloads at N ≥ 32.
PRODUCES — Local repair traces, p50/p95 latency and conflict counts.

PHASES RUN IN ORDER. P4 MAY NOT BEGIN UNTIL THE P0 NOISE FLOOR EXISTS AND THE IDENTITY TOLERANCE DERIVED FROM IT HAS BEEN FROZEN AND PUBLISHED.

Preregistered first-pass criteria · analogue system only

physical evidence: none

ID	Criterion	Locked threshold	Phase	Result
F1	Locality of every controller write	EXACTLY ZERO controller writes outside the local-neighbour rule during a valid run.	all	NO DATA
F2	False-trigger rate	Below 1% over ≥ 1,000 no-trigger trials, or the exact binomial confidence interval reported if resources limit the trial count.	P2	NO DATA
F3	Trigger success	≥ 95% inside an identified finite operating window.	P2	NO DATA
F4	Active footprint	Significantly below N, trending toward the predicted sparse-corridor behaviour as N scales.	P3, P5	NO DATA
F5	Autonomous restoration	Return to C0 without any global reset in ≥ 95% of successful runs.	P3, P4	NO DATA
F6	Payload reconstruction	Error below a baseline-specific tolerance set only after P0 noise calibration and FROZEN before P4.	P4	NO DATA
F7	Latency advantage	Exceeds measurement and control-latency uncertainty, and beats BOTH the C0 baseline and the random/local-control nulls. The global-switch positive control is allowed to be faster and is NOT the target to beat on raw speed.	P4, P6	NO DATA
F8	Scaling	Claimed only if the N-series supports the predicted DIRECTION. No asymptotic claim from N ≤ 64.	P5	NO DATA
F9	Energy separation	Electrical energy recorded separately from compute and control energy. No lumping, no subtraction.	P4, P6	NO DATA

Data schema · append-only capture

run_metaonce per run

run_id · utc_start · N · topology_hash · firmware_hash · mode (C0 | doorway | control_id) · declared thresholds · operator_blind flag

control_writeevery write, append-only

t_ns · writer_node · target_link · old_weight · new_weight · justifying_neighbour_state · address_prefix_used

node_statesynchronised ADC frame rate

t_ns · node_id · amplitude · phase · active_flag (vs declared activation band)

payloadcapture window at both ends

t_ns · component_index (≥4) · amplitude · phase · source_or_destination

energycontinuous, per rail

t_ns · rail (control | oscillator | coupling | restoration) · instantaneous_power · integrated_joules

faultper injection

t_ns · injected_element · type (link_cut | node_gate) · restored_at_ns · repairing_nodes

flowper payload, per concurrency level

flow_id · trigger_t_ns · arrival_t_ns · conflicts · p50 · p95

verdictonce per run, written after the log is sealed

metric_id (M1…M10) · locked_criterion · observed · PASS | FAIL | NOT MODELLED · auditor

Invalid-run conditions · a void run is deleted from the series, not repaired

VOIDAny controller write that reads state outside the writing node's own state and its direct neighbours.
VOIDAny globally scheduled route activation, including a precomputed per-trip path pushed to nodes.
VOIDAny destination-wide broadcast or global reset command appearing in the log.
VOIDA gap, reordering, or unsynchronised timestamp in the append-only control-write log.
VOIDAny tolerance, threshold or window changed after the preregistration hash was published.
VOIDPayload identity tolerance set or adjusted after P4 data collection began.
VOIDEnergy reported as a lumped figure, or any rail inferred by subtraction rather than measured.
VOIDFirmware changed mid-series without re-running P0 and P1 and re-hashing run_meta.

Evidence ladder · where laboratory data could and could not take us

PROTOCOL REGISTEREDREACHED

Experiment v0.1 is written, locked and published in advance of any run.

PLATFORM PRECEDENT ESTABLISHEDREACHED

Three published oscillator platforms show the required network is buildable today.

HARDWARE BUILTNOT REACHED

No components have been sourced. Nothing has been assembled.

ANALOGUE HARDWARE EFFECT OBSERVEDNOT REACHED

The first label real bench data could earn. A statement about a circuit.

REPLICATED INDEPENDENTLYNOT REACHED

Another group, another build, same preregistration.

PHYSICAL EVIDENCE FOR ADJACENCY THEORYNOT REACHED

Not reachable from this pipeline at all. A replicated electronic analogue remains an electronic analogue.

A successful v0.1 would demonstrate a PHYSICAL ANALOGUE of the localized phase-gated routing architecture. It would NOT demonstrate altered spacetime, altered distance, or faster-than-light transport of anything. Physical evidence for Adjacency Theory would remain NONE. The most that laboratory data could earn at this stage is the label ANALOGUE HARDWARE EFFECT OBSERVED — a statement about circuits.

For a ten-year-old

We found real electronic oscillator labs that can build networks like our toy world. Now we can test our moving doorway idea on actual circuits. Even if it works, it would first prove our network idea — not space travel.