Skip to content
Adjacency Theory markAdjacency Theory

Phase 74 · go for the win

Beat every road, or it is just a better road.

This page formalises the one experiment whose outcome could matter: an unpredictable payload, generated by hardware RNG only after the apparatus is armed, decoded at B and timed against D_tau — the fastest calibrated path through every measurable coupling in the machine, including clock trees, ground planes, RF leakage and software paths. Two independent timing systems, a frozen raw record, a design-only picosecond budget, nine anti-confound controls, and a ladder that ends at independent replication. Physical evidence remains NONE.

Phase 74 · go for the win · the decisive causal-bound experiment

The only measurement that could move the programme.

This is the one measurement that could matter. Map every road a message could secretly take, calibrate each road's earliest delay, then generate a brand-new secret only after the apparatus is armed — and see whether it arrives before every measured road could have carried it.

measurement architecture · design-onlyphysical evidence: none
Pioneer's Rule

SMARTER ROUTING CAN FIND A FASTER ROAD; A NEW-PHYSICS CANDIDATE REQUIRES ARRIVING BEFORE EVERY CALIBRATED ROAD COULD HAVE CARRIED NEW INFORMATION.

Foundation · what we are allowed to assume

F1Established physics
Locally interacting systems propagate information at finite speed

Lieb-Robinson-style results establish emergent finite-speed information propagation and quasi-local cone structure for broad classes of locally interacting systems.

Background framing only. We do not claim these theorems bound our oscillator bench; our envelope is measured on our own hardware.

F2Established physics
2026 oscillator platforms support arbitrary weighted/directed topologies with FPGA-controlled coupling

Reported experimental Kuramoto-type platforms allow arbitrary weighted and directed coupling under FPGA control across strong and weak regimes.

This makes the architecture test practical AND raises hidden-shortcut risk: a fabric that can wire any coupling can accidentally wire the shortcut we are trying to exclude.

F3Established physics
Architecture alone cannot beat the fastest physical causal path

The Phase 73 Frontier Theorem: under strictly local interactions and finite per-channel velocities, T_decode(B) >= D_tau(A,B) - epsilon_cal for an unpredictable post-arming payload.

The project must never claim otherwise. Any C* win over C0 that does not beat D_tau is an architecture effect.

G_phys · every measurable coupling, not just the intended ones

G_phys is the directed weighted graph over all apparatus elements whose edges are EVERY measurable coupling in classes E1-E8. Each edge e carries a calibrated earliest delay tau_e and its uncertainty sigma_e, measured on the assembled apparatus, not derived from datasheets.

E1
Analog wires / coupling lines

The intended oscillator couplings, each with its own propagation and driver delay.

Risk — Assumed to be the whole graph. They are the smallest part of it.

E2
Digital FPGA IO

Control and readout lines, serial links, LVDS pairs, IO bank timing.

Risk — IO delays vary by bank, voltage and temperature; nominal datasheet numbers are not calibration.

E3
Clock distribution

Shared reference, PLL/MMCM outputs, fanout buffers, skew between endpoints.

Risk — A shared clock tree is a direct low-latency channel between every node it reaches.

E4
Power / ground coupling

Supply rails, ground planes, decoupling networks, return-current paths.

Risk — The most commonly missed fast path. Rail sag propagates board-wide in nanoseconds.

E5
RF / capacitive / inductive leakage

Radiated and near-field coupling between traces, cables, enclosures and instruments.

Risk — Free-space propagation is the fastest available channel; it must be measured, not assumed absent.

E6
DAQ / control links

Scope probes, digitizers, trigger lines, arm/abort signals, host links.

Risk — Instruments are part of the apparatus. A trigger distribution network is an edge set.

E7
Shared buses

Backplanes, I2C/SPI chains, memory interfaces, shared FPGA fabric routing.

Risk — Two nodes on one bus are one hop apart regardless of their logical distance.

E8
Software paths

Host processes, shared memory, drivers, schedulers, logging, any code touching both endpoints.

Risk — Slow but real, and the easiest place for an accidental precomputed shortcut to hide.

D_tau(A,B) = min over physical paths P in G_phys of sum_{e in P} tau_e. The bench anomaly statistic is Delta = D_tau(A,B) - T_decode(B), where T_decode is the earliest time B decodes a newly generated unpredictable payload created at A only after the apparatus is armed.

D_tau(A,B) = min_{P : A -> B} sum_{e in P} tau_e
Delta = D_tau(A,B) - T_decode(B)
anomaly requires Delta >= 5 * sigma_total (preregistered)

Two independent stopwatches · both must agree

T1
Primary: FPGA/ASIC-style TDC

On-fabric time-to-digital conversion at the endpoints, with bin-by-bin nonlinearity calibration performed and published before data collection.

T2
Independent: external timing instrument

A separate instrument on a separate timebase, with its own cable and probe delay calibration. Both systems must agree within stated uncertainty or the run is void.

Required raw record
  • Raw edge timestamps from BOTH timing systems, unsmoothed
  • Calibration temperature and supply voltages at time of run
  • Firmware / bitstream hash (frozen before collection)
  • Topology hash and full wiring map as physically built
  • RF-isolation state (enclosure open / closed / absorber configuration)
  • Payload bits, RNG source identifier, and arming timestamp
  • Decoder output, bit error rate, and decision threshold used
  • Every controller read/write event, timestamped and attributed to a node

NO SMOOTHING-DEPENDENT ARRIVAL METRIC. Arrival is the first threshold crossing on the raw record under a frozen threshold rule. Filtering, windowing, averaging or fitting may be reported alongside but may never define T_decode.

Timing budget · DESIGN-ONLY — no instrument has been characterised

How small an advance would have to be believed

Component1-sigma (ps)
source_trigger15
timestamp_A25
timestamp_B25
cable_model20
fpga_io_cal30
environment_drift20
combined in quadrature56.3

Combined 1-sigma

~56.3 ps

Design target, not measured

Conservative 5-sigma margin

~282 ps

Preregistered anomaly threshold

Calibrated path delayRequired fractional advance
50 ns~0.563%
100 ns~0.282%
200 ns~0.141%
500 ns~0.056%
1 us~0.028%

The longer the calibrated path, the smaller the fractional advance a 5-sigma anomaly requires — which is exactly why long paths are the tempting regime and exactly why hidden fast channels (RF, clock tree, ground) must be inventoried first. A 0.028% advance over a 1 us logical path is trivially produced by one uncalibrated 300 ps leakage edge.

FPGA TDC literature reports picosecond-class RESOLUTION, but calibration and differential/integral nonlinearity remain first-class error terms. Resolution is not absolute accuracy. The budget above is a design target used to size the experiment; every term must be measured and published before it may enter an anomaly claim.

Classification ladder · fixed before any data exists

RUNG 1ARCHITECTURE / LATENT-CONNECTIVITY EFFECT
T_C* < T_C0 but T_C* >= D_tau - uncertainty

The doorway beat the intended logical route by exploiting physical connectivity the logical route ignored. Good engineering, zero physical novelty, and the expected outcome.

RUNG 2NO ANOMALY
T_C* consistent with D_tau within uncertainty

The apparatus behaves exactly as its measured causal graph predicts. Report and move on.

RUNG 3CAUSAL-BOUND ANOMALY CANDIDATE
T_C* < D_tau by preregistered >= 5 sigma, unpredictable payload decodes above threshold, zero prohibited channels, dual-timing agreement, blinded analysis

A candidate, not a discovery. The prior remains that an uninventoried channel or a calibration systematic explains it. Publish raw data, channel inventory and firmware hash immediately and invite attack.

RUNG 4INDEPENDENT REPLICATION REQUIRED BEFORE ANY STRONGER INTERPRETATION
Rung 3 replicated on an independently built apparatus by an independent team

Only after independent replication may the result be discussed as anything beyond an apparatus anomaly. Even then, no FTL and no spacetime language on this site.

Anti-confound controls · all mandatory

K1
RF enclosure / absorber comparison

Runs repeated shielded, unshielded and with absorber. The fastest configuration bounds the apparatus.

K2
Isolated battery supplies

Endpoints on independent battery power to break shared-rail and ground-return coupling.

K3
Optical isolation where possible

Fibre or optocoupled links on control and trigger paths, with the isolator delay separately calibrated.

K4
Randomized physical wiring after firmware freeze

Cables and node identities permuted after the bitstream hash is locked, so no layout artefact or lookup can key off identity.

K5
Deliberately hidden shortcut positive control

A real fast link installed without the analyst's knowledge. The audit must detect it; if it does not, no run on that apparatus counts.

K6
Fake timing-offset injection

Known artificial offsets injected into the record to verify the analysis reports them at the right size and sign.

K7
Hardware-RNG payload generated after arming

The payload cannot exist before the race starts, so no cache, scheduler or precomputed table can help.

K8
Destination decoder blinded to source bits

The decoder at B is analysed without access to the transmitted sequence until after the record is sealed.

K9
Cross-correlation is not information transfer

Correlated oscillation, phase alignment or synchronisation scores nothing. The payload must DECODE above a preregistered error threshold.

Quantum note — entanglement is not a loophole

Standard quantum theory is no-signaling: entanglement alone cannot transmit information, and teleportation requires a classical channel that is itself bounded by the same calibrated delays. No quantum resource in or near this apparatus provides an exemption from D_tau, and we will not invoke one.

For a ten-year-old

First we map every road a message could secretly take. Then we send a brand-new secret number after the race starts. If the number reaches the finish before even the fastest measured road could carry it, and two stopwatches agree, that is when we ask other labs to repeat it.