Experiment v0.1 · preregistered bench protocol · locked
We wrote down exactly how the machine could prove us wrong — before we built the machine.
No new mechanism is proposed on this page. It fixes, in advance, what the bench must do: five phases from calibration to autonomous restoration, seven controls including a deliberately cheating one, fifteen primary endpoints with frozen definitions, ten proposed pass thresholds at N = 16, 32 and 64, the instrumentation channels, the rules that void a run outright, and the raw data that must be published for every run — including the failures.
Status
proposed thresholds · not measured resultsBENCH PROTOCOL LOCKED · HARDWARE DATA NOT YET COLLECTED · PHYSICAL EVIDENCE NONE
Programmable electronic oscillator network, or hybrid analog oscillators with FPGA-computed coupling, on a bounded-degree sparse substrate. Analogue testbed only.
Phases
5
C0 → trigger → doorway → payload → restoration
Controls
7
A → G, including the cheating positive control
Primary endpoints
15
definitions frozen
Physical evidence
NONE
This protocol is frozen. Any change to a threshold, a window, a control, or an endpoint definition after data collection begins voids the affected series and must be published as an amendment with its own timestamp.
Protocol phases 1 → 5
- PHASE 1C0 baseline
Ordinary local sparse coupling only. No doorway logic enabled anywhere on the substrate.
propagation latencyspectral responsenoise floorelectrical energyfalse-trigger rate - PHASE 2Trigger
A single local seed injected above the preregistered amplitude threshold. NO global path command of any kind is issued.
trigger thresholdhysteresis / operating windowrecruitment curve - PHASE 3C* moving doorway
Local threshold and recovery law plus compact local address logic may alter ONLY adjacent coupling state, and only as a function of that node's own state and the destination address it already holds. Every controller write and event is timestamped and auditable.
max active fractiontotal active node-timecontroller writes with origincorridor trace - PHASE 4Payload
A structured waveform carrying at least four independent components or symbols is injected at A. The destination decoder is blinded to condition wherever practical.
payload latency from trigger timestamp to decoded arrivalsymbol error rateidentity error - PHASE 5Restoration
All local coupling states return to C0 autonomously. No global reset is permitted at any point.
restoration durationresidual coupling deviation from C0autonomous restoration rate
Controls A → G
| # | Control | Purpose | Preregistered expectation |
|---|---|---|---|
| A | C0 ordinary baseline | The reference latency and energy for the same A/B pair. | Defines the denominator of Q_time. Must be beaten. |
| B | Global fast-path positive control | An explicit cheating control that switches a direct path centrally. | Allowed to be the fastest condition. Beating it on raw speed is NOT the target and would be suspicious. |
| C | Random local switching | Matched for number of switch events and energy, but with no address logic. | The null the doorway must beat. If it is not beaten, there is no result. |
| D | Trigger below threshold | Establishes the false-trigger rate and the lower edge of the window. | Should almost never recruit a corridor. |
| E | Destination-label shuffle | Addresses randomly permuted while everything else is held fixed. | Advantage should collapse. If it does not, the address logic is not doing the work. |
| F | Address disabled | Local threshold/recovery law with no address guidance at all. | Isolates how much of any advantage is addressing versus excitability. |
| G | Fault injection | Edge failure, node failure, or address corruption injected mid-run. | Quantifies robustness and added latency, not headline performance. |
Primary endpoints · preregistered definitions
| Endpoint | Definition | Unit | Value |
|---|---|---|---|
| valid_run_rate | Counted runs surviving every invalid-run rule, over all attempted runs. | fraction | NO DATA |
| trigger_threshold | Seed amplitude at 50% recruitment, plus the hysteresis / operating window edges. | V (and window in V) | NO DATA |
| false_trigger_rate | Corridor recruitment observed with no trigger applied, or below the threshold window. | fraction | NO DATA |
| max_active_fraction | Peak simultaneously active nodes divided by N, over the run. | fraction of N | NO DATA |
| total_active_node_time | Integral of active node count over the run duration. | node·s | NO DATA |
| payload_latency | Trigger timestamp to decoded arrival at B. | s | NO DATA |
| C0_latency | Ordinary-phase latency for the SAME A/B pair on the same hardware. | s | NO DATA |
| Q_time | C0_latency / payload_latency. Reported with measurement uncertainty attached. | ratio | NO DATA |
| payload_identity_error | Component-wise reconstruction error and symbol error rate at the decoder. | error / SER | NO DATA |
| restoration_duration | Decoded arrival to full autonomous return of every local coupling state to C0. | s | NO DATA |
| electrical_energy | Substrate electrical energy from trigger through restoration. | J | NO DATA |
| control_plane_energy | Controller / FPGA energy and total control message count, recorded SEPARATELY. | J, count | NO DATA |
| illicit_nonlocal_write_count | Controller writes violating the local-neighbour rule. MUST BE 0. | count | NO DATA |
| fault_recovery_success | Successful reroute rate and added latency under injected faults. | fraction, s | NO DATA |
| concurrent_latency_tail | p95 and p99 latency under multiple simultaneous payloads. | s | NO DATA |
First-pass criteria · N = 16 / 32 / 64
proposed thresholds · not measured results| # | Criterion | N = 16 | N = 32 | N = 64 |
|---|---|---|---|---|
| 1 | illicit_nonlocal_write_count on every counted run | = 0 | = 0 | = 0 |
| 2 | false-trigger rate, ≥ 100 baseline/control trials per configuration | ≤ 1% | ≤ 1% | ≤ 1% |
| 3 | trigger success above the frozen threshold window | ≥ 95% | ≥ 95% | ≥ 95% |
| 4 | payload identity / symbol success on clean runs | ≥ 99% | ≥ 99% | ≥ 99% |
| 5 | autonomous restoration without global reset | ≥ 99% | ≥ 99% | ≥ 99% |
| 6 | max_active_fraction (amendable only BEFORE data) | ≤ 0.35 | ≤ 0.20 | ≤ 0.12 |
| 7 | Q_time planning target — report exact observed values regardless | > 1 | > 1.5 | > 2.5 |
| 8 | electrical + control-plane energy reported, favourable or not | reported | reported | reported |
| 9 | successful reroute under one injected edge failure, mature configuration | ≥ 90% | ≥ 90% | ≥ 90% |
| 10 | qualitative claim of new physics from v0.1 | NONE | NONE | NONE |
- — Criterion 7 is a PLANNING TARGET. Any latency advantage must additionally exceed measurement uncertainty AND beat the matched random-switch control C. Beating C0 alone is not sufficient.
- — Criterion 8 permits no energy-pass claim of any kind until total energy is compared against a defined baseline task on the same hardware.
- — All thresholds on this table are PROPOSED and were fixed before any component was purchased. They are not measurements.
Instrumentation channels
| Channel | What is captured | Rate / coverage |
|---|---|---|
| OSC | Per-node oscillator voltage / quadrature phase | ≥ 20× node characteristic frequency, all N nodes |
| STATE | Local c_i (corridor) and r_i (recovery) state per node | every local-law tick |
| COUPLE | Per-edge coupling gain / switch state | on change, plus periodic full snapshot |
| WRITE | Every controller write: source node, destination edge, value, timestamp, origin flag | append-only, on event |
| TRIG | Trigger waveform as injected at A | full capture |
| PAY | Payload waveform at A and decoded output at B | full capture, both ends |
| PWR | Substrate current/voltage traces and control-plane rail, separated | ≥ 1 kHz, independent rails |
| ADDR | Compact address state held at each node | snapshot pre-run and post-run, plus on corruption events |
| FAULT | Injected edge/node/address faults with timestamps | on event |
| META | Topology and seed, software/FPGA git hash and config, environmental metadata | once per run, hashed |
Invalid-run rules · the run is void, not repaired
- VOIDA nonlocal controller write directly configures the full route.
- VOIDA destination beacon is broadcast across all nodes.
- VOIDGlobal fast-path switching is used during a counted run.
- VOIDA hidden precomputed shortest-path sequence is pushed to all nodes.
- VOIDAny manual intervention after the trigger.
- VOIDMissing timestamps or missing log segments.
Required raw-data export · per run
Raw exports are published for every counted run, including invalid and failed runs, with the invalidating condition named. A run that is not exported did not happen.
Scaling rule
Advance N = 16 → 32 → 64 only if the previous size passes the validity, identity and restoration gates (criteria 1, 4 and 5).
Fit latency, active footprint, energy and control overhead against N.
No O(log N) claim from three points. Any statement about scaling is a FINITE-SIZE TREND over N ∈ {16, 32, 64} and must be written as such.
What would falsify us?
Written before the bench exists. Any one of these conditions ends the v0.1 claim; none of them can be argued away after the fact.
The architecture is a centralized switch with extra steps. The local claim is dead.
The address logic contributes nothing; the effect is switching activity, not routing structure.
Any speed-up is bought, not earned. Reported as a FAIL, not as a trade-off.
The corridor is a fragile coincidence of one address assignment.
The doorway is not autonomous and the two-phase structure is not realized.
We report that we built a switched network. That is the honest outcome and it stays on the site.
For a ten-year-old
Now we stop changing the idea. We write down exactly what the machine must do before we build it, so we cannot change the rules after seeing the answer. If the machine fails, we learn. If it passes, we build a bigger one.