Phase 76 · verified results → engineering transition
Seven gates before a single thing is built.
This page governs the moment the programme would be most tempted to fool itself: the first time an apparatus produces an interesting number. It defines the verification ladder from a frozen protocol through delay scaling, apparatus permutation, independent timing, an independently assembled second apparatus and finally external replication — plus the two-tier engineering handoff, the permanent separation between the frozen golden metrology rig and the optimised engineering rig, and eight hard metrics that must read green before any of it unlocks. Every rung is unstarted and every metric is pending. Physical evidence remains NONE.
Phase 76 · verified results → engineering transition
Nothing gets engineered on the strength of a hopeful reading.
A single machine blinking early is not a result. This page defines the seven rungs that must be cleared before anything is engineered, the exact point at which engineering is allowed to start, and the permanent separation between the frozen rig that proves the claim and the optimised rig that scales it.
Engineering begins only after the full causal-bound protocol is cleared with reproducible hardware data. Optimisation is not permitted to touch the frozen verification device until its baseline is archived and independently reproduced. Every rung below is a gate, not a milestone: failing one returns the programme to the rung below it, not forward with a caveat.
The verification ladder · V0 → V6
Each rung is a gate. Failing one returns the programme to the rung below, never forward with a caveat.
Nothing is measured until the whole decision apparatus is immutable and hashed. A protocol that can still be edited cannot produce a result.
- Firmware/bitstream hash published
- Analysis code hash published
- Exclusion criteria written and frozen
- Timing architecture fully specified
- Causal graph channel inventory complete
- Hidden-shortcut positive controls prepared
The preregistered outcome must recur on the same apparatus across repeated, blinded runs — not once, and not with the operator knowing the condition.
- Repeated runs on the same apparatus
- Blinded condition labels
- Hardware-generated unpredictable payload created after arming
- Full raw timestamps and waveforms retained unsmoothed
Repeat across multiple calibrated causal delays — additional optical delay segments or equivalent. A fixed instrumentation offset cannot follow the inserted delay; the margin must remain outside the conservative causal envelope at every setting.
- At least three distinct calibrated delay settings
- Envelope recomputed empirically per setting, never from nominal length
- Margin outside the conservative envelope at EVERY setting
- Cable-swap null run at each setting
Randomised wiring and topology relabeling applied after the firmware freeze. The effect must follow the hypothesised dynamics, not particular ports, cables or node identities.
- Permutations drawn after the firmware hash is locked
- Effect tracks the dynamical role, not the physical port
- No permutation in which the effect vanishes without an explanation the model already made
Two timing systems that do not share a calibration model, a reference chain, or a data path must agree within their stated uncertainties.
- Two independent measurement stacks
- No shared hidden timing or data path between them
- Disagreement beyond stated uncertainty auto-invalidates the run set
A second, independently assembled apparatus reproduces the preregistered result from the frozen protocol.
- Second apparatus built from the specification, not cloned from the first
- Same preregistered analysis, same thresholds, no re-tuning
- Both raw datasets published with hashes
Another team, in another lab, reproduces the result working only from the published protocol and parts specification, with no involvement from us during data collection.
- Independent team, independent parts procurement
- Blinded analysis run by that team
- Result published with their own raw data
Even a fully cleared V6 buys exactly one sentence: a reproducible anomaly relative to a calibrated causal envelope exists in this class of apparatus. It does not identify a mechanism, does not imply superluminal signalling, and does not touch spacetime. Any stronger reading would be us breaking our own rules.
Engineering handoff · when work may begin
- — Architecture and reliability improvements on a separate rig
- — Fault tolerance, throughput and address-fabric work
- — Build-out of tooling, automation and data pipelines
- — Any modification to the frozen verification device
- — Treating Tier 1 as evidence of an anomaly — it is evidence of a stable measurement
- — Publishing the improved rig's numbers as verification data
- — A dedicated engineering program to characterise the anomaly's dependence on delay, topology, scale and environment
- — Design of purpose-built instruments to map the effect
- — Open publication of the parts specification for wider replication
- — Mechanism claims without a physical theory
- — FTL, signalling or spacetime language
- — Retiring the golden rig
Never optimise the apparatus in a way that changes the frozen verification device before the frozen baseline has been archived and reproduced. Optimisation that touches the device under test destroys the evidence it was meant to strengthen.
Two branches · golden metrology rig vs engineering rig
Prove or refute the claim. Nothing else.
- — Frozen: firmware, wiring map, analysis code all hashed
- — Minimal: the fewest components that can carry the test
- — Auditable: every channel inventoried, every read attributed
- — Archived: full raw dataset and configuration preserved before any change
Changes are forbidden while the baseline is unreproduced. Any change forks a new golden rig with its own baseline and its own ladder from V0.
Scale, optimise, harden. Never a source of verification data.
- — Optimised for throughput, cost and reliability
- — Free to change continuously
- — May diverge arbitrarily from the golden configuration
- — Numbers from this rig are engineering telemetry, never evidence
Change freely. Never feed its results into a verification claim.
This separation is essential and non-negotiable. The single most common way a real anomaly programme destroys itself is by improving the machine that produced the signal.
Design direction · the metrology rig
- Use deliberately large calibrated physical delays instead of picosecond knife-edge tests. The margin should be engineered to dwarf the instrumentation, not argued to exceed it.
- Install multiple independently switchable delay segments so the delay-scaling rung (V2) is a configuration change rather than a rebuild.
- Calibrate the causal envelope empirically: pulse every inventoried channel pair, take conservative lower-confidence delays, and minimise over paths.
- Adopt a distributed timing architecture as a reference design. White Rabbit is documented by CERN as delivering sub-nanosecond accuracy and picosecond-level precision across distributed systems — treat that as an example architecture and a target, never as a guarantee about our apparatus.
- Instrument temperature, supply voltage and drift continuously; timing accuracy claims without environmental logging are not auditable.
Documented performance of a timing architecture in its intended deployment is not a specification for our apparatus. Every timing figure we use must be established by our own calibration, on our own hardware, with its own uncertainty budget.
The most famous apparent faster-than-light result of the modern era — the 2011 neutrino timing measurement between CERN and Gran Sasso — was resolved not by new physics but by the timing path itself: a fault in the fibre-optic timing chain, alongside a clock oscillator issue, accounted for the apparent early arrival. White Rabbit-class timing was part of the subsequent, corrected timing campaigns. The lesson we take is blunt: the timing distribution chain is a physical channel with its own faults, and it must be inventoried, calibrated, redundantly measured and physically inspected exactly like any signal path. An unaudited timing path is the single most likely source of any early arrival we would ever see.
Hard handoff metrics · green / red dashboard
| id | metric | criterion | value | state |
|---|---|---|---|---|
| M1 | Unpredictable payload decode success | Decode of post-arming hardware-RNG payload above the preregistered error threshold | no data | pending |
| M2 | Anomaly margin Δ | Δ = D_tau,lower − T_decode,upper must be positive by the preregistered guard band | no data | pending |
| M3 | Sigma / guard band ratio | Δ ≥ max(10 · sigma_total, fixed engineering guard band) | no data | pending |
| M4 | Hidden-shortcut control detection rate | 100% of deliberately inserted bypasses detected before unblinding | no data | pending |
| M5 | Topology-permutation robustness | Effect follows hypothesised dynamics across randomized relabelings | no data | pending |
| M6 | Two-clock agreement | Independent timing stacks agree within stated uncertainty on every run | no data | pending |
| M7 | Replication count | ≥ 1 independent apparatus and ≥ 1 external lab for full claim status | 0 | pending |
| M8 | Raw-data hashes published | Every run set, firmware image, wiring map and analysis build hashed and published | no data | pending |
Engineering unlocks only when the criteria above are explicitly met and recorded. A pending metric is treated as a red metric for every gating decision. There is no partial credit and no verbal override.
Project status · stated honestly
- VERIFICATION LADDER: DEFINED, NOT STARTED. All seven rungs V0–V6 stand at not-started because no apparatus exists.
- ENGINEERING HANDOFF: LOCKED. Tier 1 requires V1–V3; Tier 2 requires V4–V6. Neither trigger is anywhere near met.
- TOY ARCHITECTURE: CONDITIONAL / UNRESOLVED. Exact-fabric concurrency and throughput debts remain open.
- PHYSICAL EVIDENCE: NONE.
For a ten-year-old
We do not build the spaceship because one machine blinked early. First we make the same test win again and again, swap the wires, change the delay, use another clock, build a second machine, and ask another team to copy it. Only then do we engineer the bigger version.